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21.1 Overview
The V
4181 includes an LCD control module that operates on the MBA bus under the Unified Memory
R
Architecture (UMA) conventions. The frame buffer resides in the main DRAM memory. This module supports an STN
LCD panel.
21.1.1 LCD interface
The V
4181 LCD controller is a UMA based controller and uses a part of DRAM memory as a frame buffer. The
R
LCD controller supports monochrome STN LCD panels having 4-bit data bus interfaces and color STN LCD panels
having 8-bit data bus interfaces. When interfacing to a color LCD panel, GPIO pins must be allocated to provide the
upper nibble of the 8-bit LCD data bus.
In monochrome mode, the LCD controller supports 1-bpp (bit per pixel) mode (mono), 2-bpp mode (4 gray levels)
and 4-bpp mode (16 gray levels). In color mode, the LCD controller supports 4-bpp mode (16 colors) and 8-bpp mode
(256 colors). The LCD controller includes a 256-entry x 18-bit color pallet. In color 8-bpp mode, the pallet is used to
select 256 colors out of possible 262,144 colors.
The LCD controller can support up to 320 x 320 pixels, and typical LCD panel horizontal/vertical resolutions are as
follows.
The LCD controller also provides power-on and power-down sequence control for the LCD panel via the VPLCD
pin, which is for LCD logic power control, and VPBIAS pin, which is for LCD bias power control. Power sequencing is
provided to prevent latch-up damage to the panel.
The LCD controller may be disabled to allow connection of an external LCDC with integrated frame buffer RAM
such as NEC Electronics' µ PD16661. When the internal LCD controller is disabled by setting the LCDGPMODE
register in the GIU, the SHCLK, LOCLK, VPLCD, and VPBIAS pins are redefined as follows:
CHAPTER 21 LCD CONTROLLER
Table 21-1. LCD Panel Resolutions (in Pixels, TYP.)
Horizontal resolution
320
320
320
240
240
240
160
160
160
User's Manual U14272EJ3V0UM
Vertical resolution
320
240
160
320
240
160
320
240
160
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