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10.5.4 Activation via DCD interrupt request
When the DCD1# signal is asserted, the PMU asserts the POWERON signal to provide an external notification
that the CPU core is being activated. After asserting the POWERON signal, the PMU checks the BATTINH signal and
then de-asserts the POWERON signal.
If the BATTINH signal is at high level, the PMU cancels the peripheral unit reset and starts the Cold Reset
sequence to activate the CPU core.
If the BATTINH signal is at low level, the PMU sets 1 to the BATTINH bit in the PMUINTREG register and then
performs another shutdown. After the CPU core is restarted, the BATTINH bit must be checked and cleared to 0 by
software.
The DCDST bit in the PMUINTREG register does not indicate whether a DCD interrupt has occurred but instead
reflects the current status of the DCD1# pin.
Cautions1. The PMU cannot recognize changes in the DCD1# signal while the POWER signal is asserted.
If the DCD1# state when the POWER signal is asserted is different from that when the POWER
signal is deasserted, the change in the DCD1# signal is detected only after the POWER signal
is deasserted. However, if the DCD1# state when the POWER signal is asserted is the same as
that when the POWER signal is deasserted, any changes in the DCD1# signal that occur while
the POWER signal is asserted are not detected.
2. The changes in the DCD1# signal are ignored while the POWERON signal is active.
3. There is no indicator which shows an activation via DCD interrupt, if DCD1# signal has already
changed from active to inactive during power-on sequence. In other words, if software can not
find activation factor and if the DCDST bit indicates that DCD1# signal is active, the above
situation occurred.
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User's Manual U14272EJ3V0UM
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