Cpu Instruction Set Overview; Cpu Instruction Formats (32-Bit Length Instruction) - NEC VR4181 mPD30181 User Manual

1.4.2 CPU instruction set overview

There are two types of CPU instructions: 32-bit length instructions (MIPS III) and 16-bit length instructions
(MIPS16). Use of the MIPS16 instructions is enabled or disabled by setting MIPS16EN pin during a reset.
For details about instruction formats and their fields in each instruction set and operation of each instruction, refer
to V 4100 Series Architecture User's Manual.
R
(1) MIPS III instructions
All the CPU instructions are 32-bit length when executing MIPS III instructions, and they are classified into three
instruction formats as shown in Figure 1-4: immediate (I type), jump (J type), and register (R type).
Figure 1-4. CPU Instruction Formats (32-Bit Length Instruction)
I - type (Immediate)
J - type (Jump)
R - type (Register)
The instruction set can be further divided into the following five groupings:
(a) Load and store instructions move data between the memory and the general-purpose registers. They are all
immediate (I-type) instructions, since the only addressing mode supported is base register plus 16-bit,
signed immediate offset.
(b) Computational instructions perform arithmetic, logical, shift, and multiply and divide operations on values in
registers. They include R-type (in which both the operands and the result are stored in registers) and I-type
(in which one operand is a 16-bit signed immediate value) formats.
(c) Jump and branch instructions change the control flow of a program. Jumps are made either to an absolute
address formed by combining a 26-bit target address with the higher bits of the program counter (J-type
format) or register-specified address (R-type format).
Branches have 16-bit offsets relative to the program counter. JAL instructions save their return address in
register 31.
(d) System control coprocessor (CP0) instructions perform operations on CP0 registers to control the memory-
management and exception-handling facilities of the processor.
(e) Special instructions perform system calls and breakpoint exceptions, or cause a branch to the general
exception-handling vector based upon the result of a comparison. These instructions occur in both R-type
and I-type formats.
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CHAPTER 1 INTRODUCTION
31 26 25 21 20
op rs rt
31 26 25
op
31 26 25 21 20
op rs rt
User's Manual U14272EJ3V0UM
16 15
immediate
target
16 15 11 10 6 5
rd sa
The format of the branch instructions is I type.
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0
0
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