Table of Contents
Advertisement
Fig. No.
14-1.
PIU Peripheral Block Diagram .................................................................................................................... 276
14-2.
Coordinate Detection Equivalent Circuits .................................................................................................... 277
14-3.
Internal Block Diagram of PIU ..................................................................................................................... 277
14-4.
Scan Sequencer State Transition Diagram ................................................................................................. 278
14-5.
Interval Times and States ........................................................................................................................... 286
14-6.
Touch/Release Detection Timing ................................................................................................................ 298
14-7.
A/D Port Scan Timing .................................................................................................................................. 298
15-1.
Speaker Output and AUDIOOUT Pin .......................................................................................................... 315
15-2.
AUDIOIN Pin and Microphone Operation .................................................................................................... 316
16-1.
SCANOUT Signal Output Timing ................................................................................................................ 319
17-1.
CompactFlash Interrupt Logic ..................................................................................................................... 333
17-2.
Mapping of CompactFlash Memory Space ................................................................................................. 350
17-3.
Mapping of CompactFlash I/O Space ......................................................................................................... 351
19-1.
SIU1 Block Diagram .................................................................................................................................... 360
20-1.
SIU2 Block Diagram .................................................................................................................................... 379
21-1.
LCD Controller Block Diagram .................................................................................................................... 401
21-2.
View Rectangle and Horizontal/Vertical Blank ............................................................................................ 402
21-3.
Position of Load Clock (LOCLK) ................................................................................................................. 403
21-4.
Position of Frame Clock (FLM) ................................................................................................................... 404
21-5.
Monochrome Panel ..................................................................................................................................... 408
21-6.
Color Panel in 8-Bit Data Bus ..................................................................................................................... 409
21-7.
Load Clock (LOCLK) ................................................................................................................................... 410
21-8.
Frame Clock (FLM) ..................................................................................................................................... 410
21-9.
LCD Timing Parameters .............................................................................................................................. 411
21-10.
FLM Period .................................................................................................................................................. 411
22-1.
Example of Connection of PLL Passive Components ................................................................................. 430
A-1.
Mask Circuit for RSTSW# Signal ................................................................................................................ 436
A-2.
Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM) .............................................................. 437
A-3.
Release of Self-Refresh Mode by RSTSW# Signal (SDRAM) .................................................................... 438
26
LIST OF FIGURES (3/3)
Title
User's Manual U14272EJ3V0UM
Page
Advertisement
Table of Contents
