Piucmdreg (0X0B00 012A) - NEC VR4181 mPD30181 User Manual

64-/32-bit microprocessor hardware
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14.3.5 PIUCMDREG (0x0B00 012A)

Bit
15
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
7
Name
TPYD1
R/W
R/W
RTCRST
0
Other resets
0
Bit
Name
15 to 13
Reserved
12
STABLEON
11, 10
TPYEN(1:0)
9, 8
TPXEN(1:0)
7, 6
TPYD(1:0)
5, 4
TPXD(1:0)
Remark
L: low level, H: high level
CHAPTER 14 TOUCH PANEL INTERFACE UNIT (PIU)
14
13
Reserved
Reserved
STABLEON
R
R
0
0
0
0
6
5
TPYD0
TPXD1
R/W
R/W
0
0
0
0
0 is returned when read
Touch panel voltage stabilization wait time (STABLE(5:0) of PIUSTBLREG) enable
during command scan
1 : Wait for panel voltage stabilization time
0 : Ignore panel voltage stabilization time (wait time = 0)
TPY port input/output switching during command scan
11 : TPY1 output, TPY0 output
10 : TPY1 output, TPY0 input
01 : TPY1 input, TPY0 output
00 : TPY1 input, TPY0 input
TPX port input/output switching during command scan
11 : TPX1 output, TPX0 output
10 : TPX1 output, TPX0 input
01 : TPX1 input, TPX0 output
00 : TPX1 input, TPX0 input
TPY output level during command scan
11 : TPY1 = "H", TPY0 = "H"
10 : TPY1 = "H", TPY0 = "L"
01 : TPY1 = "L", TPY0 = "H"
00 : TPY1 = "L", TPY0 = "L"
TPX output level during command scan
11 : TPX1 = "H", TPX0 = "H"
10 : TPX1 = "H", TPX0 = "L"
01 : TPX1 = "L", TPX0 = "H"
00 : TPX1 = "L", TPX0 = "L"
User's Manual U14272EJ3V0UM
12
11
TPYEN1
TPYEN0
R/W
R/W
0
0
0
0
4
3
TPXD0
ADCMD3
ADCMD2
R/W
R/W
0
1
0
1
Function
10
9
TPXEN1
TPXEN0
R/W
R/W
R/W
0
0
0
0
2
1
ADCMD1
ADCMD0
R/W
R/W
R/W
1
1
1
1
(1/2)
8
0
0
0
1
1
287

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