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10.7.4 PMUDIVREG (0x0B00 00AC)
Bit
15
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
7
Name
Reserved
R/W
R
RTCRST
0
Other resets
0
Bit
Name
15 to 3
Reserved
2 to 0
DIV(2:0)
Note Holds the value before reset
This register is used to set CPU core's Div mode. The Div mode setting determines the division rate of the TClock
in relation to the pipeline clock (PClock) frequency.
Since the contents of this register are cleared to 0 during an RTC reset, the Div mode setting always DIV2 mode
just after RTC reset.
Though the Div mode has been set via this register, the setting does not become effective immediately in the
processor's operations. In order to change Div mode, software has to put the CPU core into the Hibernate mode. The
Div mode will change when the CPU core wakes up from the Hibernate mode.
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CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
14
13
Reserved
Reserved
Reserved
R
R
0
0
0
0
6
5
Reserved
Reserved
Reserved
R
R
0
0
0
0
0 is returned when read
Divide mode
111 : RFU
110 : RFU
101 : RFU
100 : RFU
011 : DIV3 mode
010 : DIV2 mode
001 : DIV1 mode
000 : Default mode (DIV2)
User's Manual U14272EJ3V0UM
12
11
10
Reserved
Reserved
R
R
R
0
0
0
0
0
0
4
3
2
Reserved
DIV2
R
R
R/W
0
0
0
0
0
Note
Function
9
8
Reserved
Reserved
R
R
0
0
0
0
1
0
DIV1
DIV0
R/W
R/W
0
0
Note
Note
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