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10.6.5 Entering Suspend mode (EDO DRAM)
<1> Stop operations of the DMA controller and LCD controller.
<2> Set registers in the ICU and CP0 to allow notification of the interrupt requests used as wake-up events to
Fullspeed mode to the CPU core.
<3> Copy the codes for the Suspend mode (<4> through <11> below) beginning at a 16-byte boundary into
the cache by using a Fill operation of CACHE instruction, and jump to the cached codes.
<4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge.
<5> If DRAM can accept mixed use of burst and distributive CBR refresh, set a value that determines the
refresh count to every 250 ns to the BCURFCNTREG register in the MBA Host Bridge. Then execute
CBR refresh cycles for a specific time period (i.e. 0x3FFF × TClock period + burst refresh interval
required by DRAM).
<6> Set 0x3FF to the BCURFCNTREG register in the MBA Host Bridge that determines refresh interval to
maximum to prevent an interruption of a Suspend mode sequence.
<7> Set the SUSPEND bit in the DRAMHIBCTL register to 1. If the BstRefr bit of the MEMCFG_REG register
in the memory controller to 1, the memory controller performs a burst refresh cycle and then put the
DRAM into self-refresh mode.
<8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller completes
a burst refresh cycle and put the DRAM into self-refresh mode.
<9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory
controller.
<10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched.
<11> Execute a SUSPEND instruction.
Caution When entering Suspend mode, set the BEV bit of the Status register in the CP0 of the CPU core
to 1 to make sure that the vector of the exception handler points the ROM area.
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User's Manual U14272EJ3V0UM
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