NEC VR4181 mPD30181 User Manual page 9

64-/32-bit microprocessor hardware
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p. 333
Modification of signal names in Figure 17-1. CompactFlash Interrupt Logic
p. 333
Modification of description for bit 0 in 17.3.3 CFG_REG_1 (0x0B00 08FE)
p. 336
Addition of Caution for bit 4 in 17.4.3 PWRRSETDRV (Index: 0x02)
Modification of description for bit 7 in 17.4.4 ITGENCREG (Index: 0x03)
p. 337
p. 338
Modification of description and addition of Caution for bit 0 in 17.4.5 CDSTCHGREG (Index: 0x04)
p. 341
Modification of descriptions for bits 7, 4, 3, and 0 in 17.4.8 IOCTRL_REG (Index: 0x07)
p. 344
Modification of description for bit 6 in 17.4.14 MEMWIDn_REG (Index: 0x11, 0x19, 0x21, 0x29,
0x31)
p. 345
Modification of description for bits 7 and 6 and addition of description in 17.4.16 MEMSELn_REG
(Index: 0x13, 0x1B, 0x23, 0x2B, 0x33)
p. 346
Addition of description in 17.4.17 MEMOFFLnREG (Index: 0x14, 0x1C, 0x24, 0x2C, 0x34)
Modification of Remark for bits 5 to 0 in 17.4.18 MEMOFFHnREG (Index: 0x15, 0x1D, 0x25, 0x2D,
p. 346
0x35)
Modification of description for bit 2 in 17.4.20 GLOCTRLREG (Index: 0x1E)
p. 348
p. 349
Modification of description for bits 1 and 0 and addition of description in 17.4.22 VOLTSELREG
(Index: 0x2F)
pp. 350, 351
Addition of 17.5 Memory Mapping of CompactFlash Card
p. 352
Addition of 17.6 Controlling Bus When CompactFlash Card Is Used
p. 356
Addition of function for bit 2 in 18.2.3 LEDCNTREG (0x0B00 0248)
p. 357
Modification of description in 18.2.4 LEDASTCREG (0x0B00 024A)
p. 359
Modification of figure in 18.3 Operation Flow
p. 360
Addition of Caution in 19.1 General
Modification of description in Table 19-1. SIU1 Registers
p. 361
pp. 362, 364, 376
Modification of values at reset in 19.3.1 through 19.3.3, 19.3.5, and 19.3.12
p. 365
Addition of description in Table 19-2. Correspondence between Baud Rates and Divisors
p. 368
Modification of descriptions for bits 2 to 0 in 19.3.7 SIUFC_1 (0x0C00 0012: Write)
Modification of R/W and addition of description in 19.3.10 SIULS_1 (0x0C00 0015)
p. 373
p. 375
Modification of descriptions for bits 7 to 4 in 19.3.11 SIUMS_1 (0x0C00 0016)
p. 377
Modification of R/W for bit 1 in 19.3.14 SIUACTMSK_1 (0x0C00 001C)
p. 379
Addition of description and Caution in 20.1 General
Modification of description in Table 20-1. SIU2 Registers
p. 380
pp. 381, 383, 395
Modification of values at reset in 20.3.1 through 20.3.3, 20.3.5, and 20.3.12
p. 384
Addition of description in Table 20-2. Correspondence between Baud Rates and Divisors
p. 387
Modification of descriptions for bits 2 to 0 in 20.3.7 SIUFC_2 (0x0C00 0002: Write)
Modification of R/W and addition of description in 20.3.10 SIULS_2 (0x0C00 0005)
p. 392
p. 394
Modification of descriptions for bits 7 to 4 in 20.3.11 SIUMS_2 (0x0C00 0006)
p. 395
Addition of description in 20.3.13 SIUIRSEL_2 (0x0C00 008)
p. 397
Modification of R/W for bit 1 in 20.3.16 SIUACTMSK_2 (0x0C00 000C)
Major Revisions in This Edition (4/5)
User's Manual U14272EJ3V0UM
Description
9

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