Table of Contents
Advertisement
5.1.1 RTC reset
During power-on, set the RTCRST# pin as active. After waiting about 600 ms for the 32.768 kHz oscillator to begin
oscillating when the power supply is stable at 3.0 V or above, setting the RTCRST# pin as inactive causes the RTC
unit to begin counting. Then, the states of the MIPS16EN and CLKSEL(2:0) pins are read after one RTC cycle. Next,
the V
4181 asserts the POWERON pin and checks the state of the BATTINH/BATTINT# signal. If it is at high level,
R
the V
4181 asserts the MPOWER pin and activates the external agent's DC/DC converter. After the stabilization time
R
period (about 350 ms) of the DC/DC converter, the V
about 16 ms following the start of PLL oscillation is required for stabilization of PLL oscillation).
An RTC reset does not save any of the status information and it completely initializes the processor's internal
state. Since the DRAM is not switched to self refresh mode, the contents of DRAM after an RTC reset are not at all
guaranteed.
After a reset, the processor becomes the system bus master, which executes a Cold Reset exception sequence
and begins to access the reset exception vectors in the ROM space. Since only part of the internal status is reset
when a reset occurs in the V
Initialization).
After power-on, the processor's pin statuses are undefined since the RTCRST# is asserted, until the 32.768 kHz
clock oscillator starts oscillation. The pin statuses after oscillation starts are described in CHAPTER 2 PIN
FUNCTIONS in this document.
RTCRST# (Input)
POWER (Input)
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal)
PLL (Internal)
RTC (Internal,
32.768 kHz)
Undefined
Note MasterClock is the basic clock used in the CPU core. Its frequency is one forth of TClock frequency.
CHAPTER 5 INITIALIZATION INTERFACE
4181 begins PLL oscillation and starts all clocks (a period of
R
4181, the processor should be completely initialized by software (see 5.4 Notes on
R
Figure 5-1. RTC Reset
L
Stable oscillation
> 32 ms
> 600 ms
User's Manual U14272EJ3V0UM
Stable oscillation
Undefined
16 ms
350 ms
16MasterClock
Note
97
Advertisement
Table of Contents
