Transmit And Receive Fifos; Csi Registers - NEC VR4181 mPD30181 User Manual

8.2.4 Transmit and receive FIFOs

The CSI contains two 8-deep 16-bit FIFOs. One is for transmission and the other for reception. The transmit and
receive shift registers access the FIFOs by 8 bits at a time. The CPU core accesses the FIFOs in either 8-bit or 16-bit
units.
The threshold of each FIFO is independently programmable. For the transmit FIFO, an interrupt request is
generated to inform the CPU that 1, 2, or 4 16-bit words are empty in the FIFO. For the receive FIFO, an interrupt
request is generated to inform the CPU core that 1, 2, or 4 16-bit words can be read from the FIFO.
The FIFO control logic can also generate interrupt requests to signal an overrun condition for the receive FIFO or
an underrun condition for the transmit FIFO. An overrun occurs when the receive shift register attempts to transfer
data to a location in the FIFO which has not be read by the CPU core. An underrun occurs when the transmit shift
register attempts to load a value from the FIFO which has not been updated by the CPU core.
(1) Overrun/underrun errors
When an overrun error occurs, the receive FIFO logic generates an overrun interrupt request if unmasked, and
overwrites the next location in the FIFO with the contents of the receive shift register.
When an underrun error occurs, the transmit FIFO logic generates an underrun interrupt request if unmasked,
and reloads the transmit shift register with the contents of the next location in the FIFO.
The software must recover the data loss caused by the overrun or underrun error.

8.3 CSI Registers

The CSI provides the following registers:
Physical address R/W
0x0B00 0900 R/W
0x0B00 0902 R
0x0B00 0904 R/W
0x0B00 0906 R/W
0x0B00 0908 R/W
0x0B00 090A R/W
0x0B00 090C R/W
0x0B00 090E R/W
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CHAPTER 8 CLOCKED SERIAL INTERFACE UNIT (CSI)
Table 8-1. CSI Registers
Register symbol
CSIMODE CSI mode register
CSIRXDATA CSI receive data register
CSITXDATA CSI transmit data register
CSILSTAT CSI line status register
CSIINTMSK CSI interrupt mask register
CSIINTSTAT CSI interrupt status register
CSITXBLEN CSI transmit burst length register
CSIRXBLEN CSI receive burst length register
User's Manual U14272EJ3V0UM
Function