Palette; Frame Buffer Memory And Fifo - NEC VR4181 mPD30181 User Manual

21.3.3 Palette

The Col(1:0) bits of the LCDCFGREG0 register indicate the desired color depth. If they are set to 0, then a
monochrome image can be displayed on a monochrome panel. If they are set 1, then a 4-shade gray scale image
can be displayed on a monochrome panel. If they are set to 2 or 3, then a palette is enabled, and a color panel can
be used.
The palette has 256 entries. Each entry has 18 bits and is 6-6-6 format for the RGB color. To access an entry first
store its index in the PalIndex(7:0) bits of the CPINDCTREG register, then read from or write to the PalData(17:0) bits
of the CPALDATREG register. To accelerate continuous accesses, the PalRDI bit or the PalWRI bit of the
CPINDCTREG register can be set to 1. When the PalRDI bit is set to 1, the LCD controller automatically adds 1 to
the PalIndex(7:0) bits of the CPINDCTREG register after reading from the PalData field; when the PalWRI bit is set to
1, the LCD controller automatically adds 1 to the PalIndex(7:0) bits after writing to the PalData field.
If the Col field is set to 2, then the pixel data provides only the lower half of the palette index. The upper half is
provided by the PalPage(3:0) bits of the CPINDCTREG register. Together they specify one entry in the palette.
Finally, the hpck and the gclk must be turned on before the palette is accessed.

21.3.4 Frame buffer memory and FIFO

The frame buffer is linear and supports a packed pixel format. The length of a scan line must be a multiple of 32.
The last double word of a scan line need not be completely filled. The pixels are stored in double words. The data
format of each double word depends on the color depth, as shown in the following table.
Bit
31
18 19 1A 1B 1C 1D 1E 1F 10 11 12 13 14 15 16 17 08 09 0A 0B 0C 0D 0E 0F 00 01 02 03 04 05 06 07
0C 0D 0E 0F
06 07
03
The frame buffer memory starts from the 32-bit address specified by the FBSA(31:0) bits of the FBSTADREG1
and FBSTADREG2 registers, and ends at the address specified by the FBEA(31:0) bits of the FBENDADREG1 and
FBENDADREG2 registers. The FBEA field does not necessarily show where the last pixel is stored; but it is the
address of the first 32-byte page boundary that follows the memory location where the last pixel is stored, starting
from the address set in the FBSA field. For example, if FBSA field is 0x0B00 0408, and the frame buffer occupies 235
bytes, then the FBEA field is 0x0B00 0508 (FBSA plus the ceiling of 235/32).
Data from the frame buffer is burst into the FIFO to conserve memory bandwidth. Each burst transfers 32 bytes.
The FIFO is divided into three arrays, and each burst fills exactly one array. Bursts can not cross array borders, nor
can read from and write to the same array at the same time. When the memory bandwidth is low, the FIFO bursts
only when there are only the number of double words left to be read that is displayed in the FIFOC(2:0) bits of the
LCDCTRLREG register. If the burst is not fast enough in relation to the refresh rate of the panel image, irreversible
image degradation occurs due to a lack of data to be displayed, and an interrupt request is generated. This interrupt
request can be polled from the FIFOOVERR bit of the LCDINRQREG register. It can be cleared only by stopping and
then restarting controller clocks. Because image degradation is a serious problem, the value set to the FIFOC field
should be carefully selected during development.
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CHAPTER 21 LCD CONTROLLER
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