Entering Hibernate Mode (Sdram) - NEC VR4181 mPD30181 User Manual

10.6.2 Entering Hibernate mode (SDRAM)

<1> Copy contents of all 2.5 V registers (i.e. DRAM type and configuration, ROM type and configuration, etc.)
that must be preserved during Hibernate mode into the general-purpose registers, MISCREG(0:15), in the
GIU or into external memory.
Remark 3.3 V peripheral units: PMU, GIU, LED, and RTC
2.5 V peripheral units: all peripherals except PMU, GIU, LED, and RTC
<2> Stop operations of the DMA controller and LCD controller.
<3> Copy the codes for the Hibernate mode (<4> through <12> below) beginning at a 16-byte boundary into
the cache by using a Fill operation of CACHE instruction, and jump to the cached codes.
<4> Stop all peripheral clocks by writing zero to the CMUCLKMSK register in the MBA Host Bridge.
<5> Set the BCURFCNTREG register in the MBA Host Bridge to a value that determines refresh interval to
maximum to prevent an interruption of a Hibernate mode sequence.
<6> If burst refreshes are needed, set a value that determines the refresh count to every 250 ns to the
BCURFCNTREG register in the MBA Host Bridge. Then execute CBR auto refresh cycles for a specific
time period (i.e. 0x3FFF × TClock period + burst refresh interval required by DRAM).
<7> Clear the BstRefr bit of the MEMCFG_REG register in the memory controller to 0 to disable a burst
refresh. Then set SUSPEND bit in the DRAMHIBCTL register to 1 to put the DRAM into self-refresh
mode.
<8> Poll the OK_STOP_CLK bit in the DRAMHIBCTL register to confirm that the memory controller puts the
DRAM into self-refresh mode.
<9> Set the STOP_CLK bit in the DRAMHIBCTL register to 1 to stop supplying TClock to the memory
controller.
<10> Set the DRAM_EN bit in the DRAMHIBCTL register to 1 so that the DRAM interface signals are latched.
<11> Clear the SUSPEND bit in the DRAMHIBCTL register to 0 after waiting for about 2 µ s.
<12> Execute a HIBERNATE instruction.
<13> Stop applying 2.5 V power supply when the MPOWER signal becomes low level.
Caution When entering Hibernate mode, set the BEV bit of the Status register in the CP0 of the CPU core
to 1 to make sure that the vector of the exception handler points the ROM area.
202
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
User's Manual U14272EJ3V0UM