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3.2.15 Config register (16)
The Config register specifies various configuration options selected on the V
Some configuration options, as defined by the EC and BE fields, are set by the hardware during Cold Reset and
are included in the Config register as read-only status bits for the software to access. Other configuration options
(AD, EP, and K0 fields) can be read/written and controlled by software; on Cold Reset these fields are undefined.
Since only a subset of the V
bits 14 and 13) that were variable in the V
caches are used.
The contents of the Config register are undefined after a reset so that it must be initialized by software.
Caution Be sure to set the EP field and the AD bit to 0. If they are set with any other values, the
processor may behave unexpectedly.
31 30
28 27
0
EC
EC:
System clock ratio (read only)
0 → Processor clock frequency divided by 2
1 → Processor clock frequency divided by 3
2 → Processor clock frequency divided by 4
3 to 7 → Reserved
EP:
Transfer data pattern (cache write-back pattern) setting
0 → DD: 1 word per 1 cycle
Others → Reserved
AD:
Accelerate data mode
0 → V
1 → Reserved
M16:
MIPS16 ISA mode enable/disable indication (read only)
0 → MIPS16 instruction cannot be executed
1 → MIPS16 instruction can be executed.
BE:
BigEndianMem (Endian mode indication)
0 → Little endian
1 → Reserved
CS:
Cache size mode indication (n = IC, DC)
0 → Reserved
1 → 2
IC:
Instruction cache size indication. 2
2 → 4 KB
Others → Reserved
DC:
Data cache size indication. 2
2 → 4 KB
Others → Reserved
CHAPTER 3 CP0 REGISTERS
TM
4000 Series
options are available in the V
R
4000 Series. The Config register should be initialized by software before
R
Figure 3-18. Config Register (1/2)
24 23 22 21 20 19 18 17 16 15 14 13 12 11
EP
AD
0
M16
0
1 0 BE
4000 Series compatible mode
R
(n+10)
bytes
(IC+10)
(DC+10)
bytes in the V
User's Manual U14272EJ3V0UM
4181.
R
4181, some bits are set to constants (e.g.,
R
9 8
10
CS
IC
bytes in the V
4181.
R
4181.
R
6 5
3 2
0
DC
0
K0
83
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