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5.2 Power-on Sequence
The factors that cause the V
called activation factors. There are five activation factors: assertion of the POWER pin, the DCD1# pin or the
GPIO(15:0) pins, or activation of the ElapsedTime or CompactFlash interrupt request. When an activation factor
occurs, the V
4181 asserts the POWERON pin to notify to external agents that the V
R
Three RTC clock cycles after the POWERON pin is asserted, the V
BATTINH/BATTINT# pin. If the BATTINH/BATTINT# pin's state is low, the POWERON pin is deasserted one RTC
clock after the BATTINH/BATTINT# pin check is completed, then the V
BATTINH/BATTINT# pin's state is high, the POWERON pin is deasserted and the MPOWER pin is asserted three
RTC clocks after the BATTINH/BATTINT# pin check is completed, then the V
Figure 5-6 shows a timing chart of V
due to the BATTINH/BATTINT# pin's "low" state.
Remark
While the MPOWER pin is inactive, 2.5 V power supply of the V
needed. In order to reduce leak current, it is recommended to turn on/off the 2.5 V power supply of the
V
4181 according to MPOWER pin state.
R
Figure 5-6. V
POWERON (Output)
MPOW ER (Output)
ColdReset# (Internal)
Reset# (Internal)
BATTINH/BATTINT#
(Input)
PLL (Internal)
RTC (Internal,
32.768 kHz)
102
CHAPTER 5 INITIALIZATION INTERFACE
4181 to switch from Hibernate mode or shutdown mode to Fullspeed mode are
R
4181 activation and Figure 5-7 shows a timing chart of when activation fails
R
4181 Activation Sequence (When Activation Is OK)
R
Stopped
Detection
of activation
factor
Check
BATTINH/BATTINT#
pin
User's Manual U14272EJ3V0UM
4181 is ready for power-on.
R
4181 checks the state of the
R
4181 is not activated. If the
R
4181 is activated.
R
4181 (VDD_LOGIC, VDD_PLL) is not
R
Undefined
Activation
of CPU
Stable oscillation
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