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A.2 RSTSW# in Hibernate Mode
The V
4181 may release the self-refresh mode of DRAM when the RSTSW# signal is asserted in the Hibernate
R
mode. As a result, the DRAM data may be lost.
(1) With EDO DRAM
When the RSTSW# signal goes low, the RAS# and CAS# signals go high and the self-refresh mode is released.
After that DRAM returns to the self-refresh mode. At this time, the following phenomena may occur, and the
DRAM data may be lost.
• DRAM is in the normal operation mode while the RAS# signal is high ((a) in Figure A-2) but a CBR refresh is
not executed.
• The high-level output of the CAS# signal ((b) in Figure A-2) may be a spike.
Figure A-2. Release of Self-Refresh Mode by RSTSW# Signal (EDO DRAM)
LCAS#, UCAS# (output)
APPENDIX A RESTRICTIONS ON V
RTC (internal)
RSTSW# (input)
RAS(1:0)# (output)
Exit self-refresh mode
Pulse width: (a) 30 to 60 µ s
User's Manual U14272EJ3V0UM
4181
R
(a)
(c)
(b)
Resume self-refresh mode
(b) 0 (spike) to 30 µ s
(c) 30 µ s
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