Dramhibctl (0X0B00 00B2) - NEC VR4181 mPD30181 User Manual

10.7.5 DRAMHIBCTL (0x0B00 00B2)

Bit 15
Name Reserved
R/W R
RTCRST 0
Other resets 0
Bit 7
Name Reserved
R/W R
RTCRST 0
Other resets 0
Bit Name
15 to 5 Reserved
4 Reserved
3 OK_STOP_CLK
2 STOP_CLK
1 SUSPEND
0 DRAM_EN
Note Holds the value before reset
CHAPTER 10 POWER MANAGEMENT UNIT (PMU)
14 13
Reserved Reserved Reserved
R R
0 0
0 0
6 5
Reserved Reserved Reserved
R R
0 0 Undefined
0 0 Undefined
0 is returned when read
An undefined value is returned when read
Ready to stop clocks
1 : Ready (DRAM is in self refresh mode)
0 : Not ready (MEMC is busy to do burst refresh)
Clock supply for MEMC
1 : Stop
0 : Supply
Self refresh request. This bit is for software request to MEMC to perform burst
refresh and enter self refresh mode
1 : Request
0 : Not request
DRAM interface operation enable
1 : Disabled
0 : Enabled (normal mode)
User's Manual U14272EJ3V0UM
12 11 10
Reserved Reserved
R R R
0 0 0
0 0 0
4 3 2
OK_STOP STOP
_CLK _CLK
R R R/W
0 0
Note Note
Function
9 8
Reserved Reserved
R R
0 0
0 0
1 0
SUSPEND DRAM_EN
R/W R/W
0 0
Note Note
215