Altera Cyclone IV Device Handbook page 314

1–34
Figure 1–32. Clock Distribution in Non-Bonded Channel Configuration for Transceivers in F484
and Larger Packages
Notes to
(1) High-speed clock.
(2) Low-speed clock.
(3) These PLLs have restricted clock driving capability and may not reach all connected channels. For details, refer to
Table
The transceiver datapath clocking varies in non-bonded channel configuration
depending on the PCS configuration.
Figure 1–33
each channel selects the high- and low-speed clock from one of the supported PLLs.
The high-speed clock feeds to the serializer for parallel to serial operation. The
low-speed clock feeds to the following blocks in the transmitter PCS:
■ 8B/10B encoder
■ read clock of the byte serializer
read clock of the TX phase compensation FIFO
■
Cyclone IV Device Handbook,
Volume 2
Ch3
Ch2
Transceiver
Block
Ch1
GXBL1
Ch0
Ch3
Ch2
Transceiver
Block
Ch1
GXBL0
Ch0
Figure 1–32:
1–9.
shows the datapath clocking in transmitter only operation. In this mode,
Chapter 1: Cyclone IV Transceivers Architecture
(1)
MPLL_8
(2)
TX PMA
TX PMA
TX PMA
TX PMA
MPLL_7
Not applicable in
(3)
F484 package
MPLL_6
(3)
TX PMA
TX PMA
TX PMA
TX PMA
(1)
MPLL_5
(2)
Transceiver Clocking Architecture
GPLL_2
(3)
GPLL_1
(3)
February 2015 Altera Corporation