Pci Express (Pipe) Mode - Altera Cyclone IV Device Handbook

1–52
Receiver Spread Spectrum Clocking
Asynchronous SSC is not supported in Cyclone IV devices. You can implement only
synchronous SSC for SATA, V-by-One, and Display Port protocols in Basic mode.

PCI Express (PIPE) Mode

PIPE mode provides the transceiver channel datapath configuration that supports ×1,
×2, and ×4 initial lane width for PCIe Gen1 signaling rate with PIPE interface
implementation. The Cyclone IV GX transceiver provides following features in PIPE
mode:
■ PIPE interface
■ receiver detection circuitry
■ electrical idle control
signal detect at receiver
■
■ lane synchronization with compliant state machine
■ clock rate compensation with rate match FIFO
■ Low-Latency Synchronous PCIe
■ fast recovery from P0s state
electrical idle inference
■
■ compliance pattern transmission
■ reset requirement
Figure 1–48
PIPE mode with ×1 channel configuration.
.
Figure 1–48. Transceiver Channel Datapath and Clocking when Configured in PIPE Mode with ×1 Channel Configuration
FPGA
Fabric
Notes to Figure 1–48:
(1) Low-speed recovered clock.
(2) High-speed recovered clock.
Cyclone IV Device Handbook,
Volume 2
shows the transceiver channel datapath and clocking when configured in
Tx Phase
Comp Byte Serializer
FIFO
wr_clk rd_clk wr_clk
Rx
Byte Byte
Phase
De-
Order-
Comp
ing serializer
FIFO
/2
Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel PCS
8B/10B Encoder
rd_clk
/2
Receiver Channel PCS
Rate
8B/10B Deskew
Match
Decoder FIFO
FIFO
Transceiver Functional Modes
Transmitter Channel PMA
Serializer
Receiver Channel PMA
Word Deserial-
CDR
Aligner izer
(2)
(1)
February 2015 Altera Corporation
high-speed
clock
low-speed clock
CDR clock