Altera Cyclone IV Device Handbook page 46

3–10
Table 3–3. Cyclone IV Devices M9K Block Mixed-Width Configurations (Simple Dual-Port Mode) (Part 2 of 2)
Read Port
8192 × 1 4096
v
512 × 16
v
256 × 32
1024 × 9 —
512 × 18 —
256 × 36 —
In simple dual-port mode, M9K memory blocks support separate wren and rden
signals. You can save power by keeping the rden signal low (inactive) when not
reading. Read-during-write operations to the same address can either output "Don't
Care" data at that location or output "Old Data". To choose the desired behavior, set
the Read-During-Write option to either Don't Care or Old Data in the RAM
MegaWizard Plug-In Manager in the Quartus II software. For more information about
this behavior, refer to
Figure 3–9
dual-port mode with unregistered outputs. Registering the outputs of the RAM
simply delays the q output by one clock cycle.
Figure 3–9. Cyclone IV Devices Simple Dual-Port Timing Waveform
wrclock
wren
an-1
wraddress
data
din-1
rdclock
rden
rdaddress
bn
q (asynch)
doutn-1
Cyclone IV Device Handbook,
Volume 1
× 2 2048 × 4 1024 × 8
v v v
v v v
— — —
— — —
— — —
"Read-During-Write Operations" on page
shows the timing waveform for read and write operations in simple
a0 a1
an
din
b0
doutn
Chapter 3: Memory Blocks in Cyclone IV Devices
Write Port
512 × 16 256 × 32 1024
v v
v v
— —
— —
— —
a2 a3 a4
din4
b1 b2
dout0
Memory Modes
× 9 512 × 18 256 × 36
— — —
— — —
v v v
v v v
v v v
3–15.
a5
a6
din5 din6
b3
November 2011 Altera Corporation