2–4
Arithmetic Mode
Arithmetic mode is ideal for implementing adders, counters, accumulators, and
comparators. An LE in arithmetic mode implements a 2-bit full adder and basic carry
chain
versions of the LUT output. Register feedback and register packing are supported
when LEs are used in arithmetic mode.
Figure 2–3
Figure 2–3. Cyclone IV Device LEs in Arithmetic Mode
Packed Register Input
data4
data1
data2
data3
cin (from cout
of previous LE)
The Quartus II Compiler automatically creates carry chain logic during design
processing. You can also manually create the carry chain logic during design entry.
Parameterized functions, such as LPM functions, automatically take advantage of
carry chains for the appropriate functions.
The Quartus II Compiler creates carry chains longer than 16 LEs by automatically
linking LABs in the same column. For enhanced fitting, a long carry chain runs
vertically, which allows fast horizontal connections to M9K memory blocks or
embedded multipliers through direct link interconnects. For example, if a design has a
long carry chain in an LAB column next to a column of M9K memory blocks, any LE
output can feed an adjacent M9K memory block through the direct link interconnect.
If the carry chains run horizontally, any LAB which is not next to the column of M9K
memory blocks uses other row or column interconnects to drive a M9K memory
block. A carry chain continues as far as a full column.
Cyclone IV Device Handbook,
Volume 1
(Figure
2–3). LEs in arithmetic mode can drive out registered and unregistered
shows LEs in arithmetic mode.
Register Chain
sload
Connection
Three-Input
LUT
Three-Input
LUT
clock (LAB Wide)
ena (LAB Wide)
aclr (LAB Wide)
cout
Register Bypass
Chapter 2: Logic Elements and Logic Array Blocks in Cyclone IV Devices
sclear
(LAB Wide)
(LAB Wide)
Q
D
ENA
CLRN
Register Feedback
LE Operating Modes
Row, Column, and
Direct link routing
Row, Column, and
Direct link routing
Local Routing
Register
Chain Output
November 2009 Altera Corporation
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