Software Support - Altera Cyclone IV Device Handbook

9–6
Table 9–6
maximum clock frequencies for Cyclone IV devices.
Table 9–6. CRC Calculation Time
Device
Cyclone IV E
Cyclone IV GX
Notes to Table 9–6:
(1) The minimum time corresponds to the maximum error detection clock frequency and may vary with different processes, voltages, and
temperatures (PVT).
(2) The maximum time corresponds to the minimum error detection clock frequency and may vary with different PVT.
(3) Only applicable for device with 1.2-V core voltage
(4) Only applicable for the F484 device package.

Software Support

Enabling the CRC error detection feature in the Quartus II software generates the
CRC_ERROR output to the optional dual purpose CRC_ERROR pin.
To enable the error detection feature using CRC, perform the following steps:
1. Open the Quartus II software and load a project using Cyclone IV devices.
2. On the Assignments menu, click Settings. The Settings dialog box appears.
3. In the Category list, select Device. The Device page appears.
4. Click Device and Pin Options. The Device and Pin Options dialog box appears as
shown in
5. In the Device and Pin Options dialog box, click the Error Detection CRC tab.
6. Turn on Enable error detection CRC.
7. In the Divide error check frequency by box, enter a valid divisor as documented
in
Cyclone IV Device Handbook,
Volume 1
lists the estimated time for each CRC calculation with minimum and
(3)
EP4CE6
(3)
EP4CE10
(3)
EP4CE15
(3)
EP4CE22
(3)
EP4CE30
(3)
EP4CE40
(3)
EP4CE55
(3)
EP4CE75
(3)
EP4CE115
EP4CGX15
EP4CGX22
EP4CGX30
EP4CGX50
EP4CGX75
EP4CGX110
EP4CGX150
Figure 9–2.
Table 9–5 on page 9–5.
Chapter 9: SEU Mitigation in Cyclone IV Devices
(1)
Minimum Time (ms)
5
5
7
9
15
15
23
31
45
6
12
12
(4)
34
34
34
62
62
Software Support
(2)
Maximum Time (s)
2.29
2.29
3.17
4.51
7.48
7.48
11.77
15.81
22.67
2.93
5.95
5.95
(4)
17.34
17.34
17.34
31.27
31.27
May 2013 Altera Corporation