Altera Cyclone IV Device Handbook page 485

Chapter 1: Cyclone IV Device Datasheet
Glossary
Table 1–46. Glossary (Part 3 of 5)
Letter Term
R
L
Receiver Input
Waveform
R
Receiver input
skew margin
(RSKM)
Single-ended
voltage-
referenced I/O
S
Standard
SW (Sampling
Window)
December 2016 Altera Corporation
Receiver differential input discrete resistor (external to Cyclone IV devices).
Receiver input waveform for LVDS and LVPECL differential standards:
Single-Ended Waveform
V
CM
Differential Waveform (Mathematical Function of Positive & Negative Channel)
V
ID
High-speed I/O block: The total margin left after accounting for the sampling window and TCCS.
RSKM = (TUI – SW – TCCS) / 2.
V
OH
V
OL
The JEDEC standard for SSTl and HSTL I/O standards defines both the AC and DC input signal
values. The AC values indicate the voltage levels at which the receiver must meet its timing
specifications. The DC values indicate the voltage levels at which the final logic state of the
receiver is unambiguously defined. After the receiver input crosses the AC value, the receiver
changes to the new logic state. The new logic state is then maintained as long as the input stays
beyond the DC threshold. This approach is intended to provide predictable receiver timing in the
presence of input waveform ringing.
High-speed I/O block: The period of time during which the data must be valid to capture it
correctly. The setup and hold times determine the ideal strobe position in the sampling window.
Definitions
V
ID
V
ID
V
REF
1–39
Positive Channel (p) = V
IH
Negative Channel (n) = V
IL
Ground
0 V
p - n
V
CCIO
V
IH ( AC )
V
IH(DC)
V
IL(DC)
V
IL(AC )
V
SS
Cyclone IV Device Handbook,
Volume 3