Prbs - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture
Self Test Modes

PRBS

Figure 1–74
modes. The pattern generator is located in TX PCS before the serializer, and PRBS
pattern verifier located in RX PCS after the word aligner.
Figure 1–74. PRBS Pattern Test Mode Datapath
Transceiver
FPGA
Fabric
Transmitter Channel PCS
Tx Phase
Compensation
FIFO
Receiver Channel PCS
Rx
Compensation
FIFO
Note to Figure 1–74:
(1) Serial loopback path is optional and can be enabled for the PRBS verifier to check the PRBS pattern
Table 1–25
corresponding channel settings. The PRBS pattern repeats after completing an
iteration. The number of bits a PRBS X pattern sends before repeating the pattern is
(X-1)
2
Table 1–25. PRBS, High and Low Frequency Patterns, and Channel Settings (Part 1 of 2)
Patterns Polynomial
7 6
PRBS 7 X + X + 1
8 7
PRBS 8 X + X + 1
10 7
PRBS 10 X + X + 1
23 18
PRBS 23 X + X + 1
High
1010101010
(2)
frequency
February 2015 Altera Corporation
shows the datapath for the PRBS, high and low frequency pattern test
PRBS, High Freq,
Low Freq Pattern
Byte 8B/10B
Serializer Encoder
Byte Byte
Ordering Deserializer
lists the supported PRBS, high and low frequency patterns, and
bits.
8-bit Channel Width
Maximum
Channel
Data Rate
Width Word
(Gbps) for
of Alignment
F324 and
8 bits Pattern
Smaller
(1)
Packages
Y 16'h3040
Y 16'hFF5A
N —
Y 16'hFFFF
Y —
Generator
PRBS
Verifier
Rate
8B/10B
Match
Decoder Aligner
FIFO
Maximum
Channel
Data Rate
Width
(Gbps) for
of
F484 and
10-bits
Larger
(1)
Packages
2.0 2.5 N
2.0 2.5 N
— — Y
2.0 2.5 N
2.0 2.5 Y
Transmitter Channel PMA
Serializer
(1)
Receiver Channel
PMA
De-
Receiver
Word
serializer
CDR
10-bit Channel Width
Maximum
Data Rate
Word
(Gbps) for
Alignment
F324 and
Pattern
Smaller
Packages
— —
— —
10'h3FF 2.5
— —
— 2.5
Cyclone IV Device Handbook,
1–83
Maximum
Data Rate
(Gbps) for
F484 and
Larger
Packages
—
—
3.125
—
3.125
Volume 2