Dynamic Reconfiguration Reset Sequences; Reset Sequence In Pll Reconfiguration Mode - Altera Cyclone IV Device Handbook

Chapter 2: Cyclone IV Reset Control and Power Down

Dynamic Reconfiguration Reset Sequences

Dynamic Reconfiguration Reset Sequences
When using dynamic reconfiguration in data rate divisions in PLL reconfiguration or
channel reconfiguration mode, use the following reset sequences.

Reset Sequence in PLL Reconfiguration Mode

Use the example reset sequence shown in
reconfiguration controller to change the data rate of the transceiver channel. In this
example, PLL dynamic reconfiguration is used to dynamically reconfigure the data
rate of the transceiver channel configured in Basic ×1 mode with the receiver CDR in
automatic lock mode.
Figure 2–11. Reset Sequence When Using the PLL Dynamic Reconfiguration Controller to Change
the Data Rate of the Transceiver Channel
Reset and Control Signals
Notes to
(1) The pll_configupdate and pll_areset signals are driven by the ALTPLL_RECONFIG megafunction. For more
information, refer to
Dynamic Reconfiguration
(2) For t
As shown in
dynamic reconfiguration controller to change the configuration of the PLLs in the
transmitter channel:
1. Assert the tx_digitalreset, rx_analogreset, and rx_digitalreset signals. The
pll_configupdate signal is asserted (marker 1) by the ALTPLL_RECONFIG
megafunction after the final data bit is sent out. The pll_reconfig_done signal is
asserted (marker 2) to inform the ALTPLL_RECONFIG megafunction that the scan
chain process is completed. The ALTPLL_RECONFIG megafunction then asserts
the pll_areset signal (marker 3) to reset the transceiver PLL.
September 2014 Altera Corporation
tx_digitalreset
rx_analogreset
rx_digitalreset
1
pll_configupdate (1)
pll_areset (1)
Output Status Signals
2
pll_reconfig_done
pll_locked
rx_freqlocked
Figure 2–11:
AN 609: Implementing Dynamic Reconfiguration in Cyclone IV GX Devices
chapter.
duration, refer to the Cyclone IV Device Datasheet
LTD_Auto
Figure 2–11, perform the following reset procedure when using the PLL
Figure 2–11 when you use the PLL dynamic
5
3
Five parallel clock cycles
4
chapter.
2–19
6
8
7
t (2)
LTD_Auto
and the Cyclone IV
Cyclone IV Device Handbook,
Volume 2