External Clock Outputs - Altera Cyclone IV Device Handbook

Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
Cyclone IV PLL Hardware Overview
Figure 5–10
Cyclone IV E devices.
Figure 5–10. Cyclone IV E PLL Block Diagram
4
Clock inputs
inclk0
from pins
Clock
Switchover
inclk1
Block
(3)
GCLK
pfdena
Notes to Figure 5–10:
(1) Each clock source can come from any of the four clock pins located on the same side of the device as the PLL.
(2) This is the VCO post-scale counter K.
(3) This input port is fed by a pin-driven dedicated GCLK, or through a clock control block if the clock control block is fed by an output from another
PLL or a pin-driven dedicated GCLK. An internally generated global signal cannot drive the PLL.
1
The VCO post-scale counter K is used to divide the supported VCO range by two. The
VCO frequency reported by the Quartus II software in the PLL summary section of
the compilation report takes into consideration the VCO post-scale counter value.
Therefore, if the VCO post-scale counter has a value of 2, the frequency reported is
lower than the f

External Clock Outputs

Each PLL of Cyclone IV devices supports one single-ended clock output or one
differential clock output. Only the C0 output counter can feed the dedicated external
clock outputs, as shown in
output counters can feed other I/O pins through the GCLK.
October 2012 Altera Corporation
shows a simplified block diagram of the major components of the PLL of
(1)
lock
LOCK
circuit
÷n
PFD CP LF
clkswitch
clkbad0
clkbad1
VCO
Range
activeclock
Detector
specification specified in the
VCO
Figure 5–11, without going through the GCLK. Other
÷C0
÷C1
8
8
÷2 (2)
VCO
÷C2
PLL
output
÷C3 mux
VCOOVRR
÷C4
VCOUNDR
÷M
no compensation;
ZDB mode
source-synchronous;
normal mode
Cyclone IV Device Datasheet
5–21
GCLKs
External clock output
GCLK networks
chapter.
Cyclone IV Device Handbook,
Volume 1