Altera Cyclone IV Device Handbook page 413

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
Figure 3–4
Figure 3–4. Write Transaction Waveform—Use 'logical_channel_address port' Option
reconfig_clk
rx_tx_duplex_sel [1:0]
logical_channel_address [1:0]
tx_vodctrl [2:0]
Notes to Figure 3–4:
(1) In this waveform example, you are writing to only the transmitter portion of the channel.
(2) In this waveform example, the number of channels connected to the dynamic reconfiguration controller is four. Therefore, the
logical_channel_address port is 2 bits wide.
Read Transaction
For example, to read the existing V
the transmitter portion of a specific channel controlled by the ALTGX_RECONFIG
instance, perform the following steps:
1. Set the logical_channel_address input port to the logical channel address of the
transceiver channel whose PMA controls you want to read (for example,
tx_vodctrl_out).
2. Set the rx_tx_duplex_sel port to 2'b10 so that only the transmit PMA controls are
read from the transceiver channel.
3. Ensure that the busy signal is low before you start a read transaction.
4. Assert the read signal for one reconfig_clk clock cycle. This initiates the read
transaction.
The busy output status signal is asserted high to indicate that the dynamic
reconfiguration controller is busy reading the PMA control values. When the read
transaction has completed, the busy signal goes low. The data_valid signal is asserted
to indicate that the data available at the read control signal is valid.
November 2011 Altera Corporation
shows the write transaction waveform for Method 1.
write_all
2'b00
(1)
2'b00
(2)
busy
3'b111
2'b10
2'b01
3'b001
values from the transmit V
OD
3–15
control registers of
OD
Cyclone IV Device Handbook,
Volume 2