1–54
PIPE Interface
The PIPE interface provides a standard interface between the PCIe-compliant PHY
and MAC layer as defined by the version 2.00 of the PIPE Architecture specification
for Gen1 (2.5 Gbps) signaling rate. Any core or IP implementing the PHY MAC, data
link, and transaction layers that supports PIPE 2.00 can be connected to the
Cyclone IV GX transceiver configured in PIPE mode.
ports available from the Cyclone IV GX transceiver configured in PIPE mode and the
corresponding port names in the PIPE 2.00 specification.
Table 1–15. Transceiver-FPGA Fabric Interface Ports in PIPE Mode
Transceiver Port Name
tx_datain[15..0]
tx_ctrlenable[1..0]
rx_dataout[15..0]
rx_ctrldetect[1..0]
tx_detectrxloop
tx_forceelecidle
tx_forcedispcompliance
pipe8b10binvpolarity
powerdn[1..0]
pipedatavalid
pipephydonestatus
pipeelecidle
pipestatus
Notes to
(1) When used with PCIe hard IP block, the byte SERDES is not used. In this case, the data ports are 8 bits wide and
(2) Cyclone IV GX transceivers do not implement power saving measures in lower power states (P0s, P1, and P2),
Receiver Detection Circuitry
In PIPE mode, the transmitter supports receiver detection function with a built-in
circuitry in the transmitter PMA. The PCIe protocol requires the transmitter to detect
if a receiver is present at the far end of each lane as part of the link training and
synchronization state machine sequence. This feature requires the following
conditions:
■
transmitter output buffer to be tri-stated
■
have OCT utilization
■
125 MHz clock on the fixedclk port
The circuit works by sending a pulse on the common mode of the transmitter. If an
active PCIe receiver is present at the far end, the time constant of the step voltage on
the trace is higher compared to when the receiver is not present. The circuitry
monitors the time constant of the step signal seen on the trace to decide if a receiver
was detected.
Cyclone IV Device Handbook,
Volume 2
(1)
(1)
(1)
(1)
(2)
Table
1–15:
control identifier is 1 bit wide.
except when putting the transmitter buffer in electrical idle in the lower power states.
Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Table 1–15
lists the PIPE-specific
PIPE 2.00 Port Name
TxData[15..0]
TxDataK[1..0]
RxData[15..0]
RxDataK[1..0]
TxDetectRx/Loopback
TxElecIdle
TxCompliance
RxPolarity
PowerDown[1..0]
RxValid
PhyStatus
RxElecIdle
RxStatus[2..0]
February 2015 Altera Corporation
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