Altera Cyclone IV Device Handbook page 131

Chapter 6: I/O Features in Cyclone IV Devices
High-Speed I/O Interface
Table 6–6
the Cyclone IV device family.
Table 6–6. Differential I/O Standards Supported in Cyclone IV E I/O Banks
Differential I/O Standards
LVDS
RSDS
mini-LVDS
PPDS
(1)
BLVDS
(2)
LVPECL
(3)
Differential SSTL-2
(3)
Differential SSTL-18
(3)
Differential HSTL-18
(3)
Differential HSTL-15
(3) (4)
Differential HSTL-12 ,
Notes to Table 6–6:
(1) Transmitter and Receiver f
MAX
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
(4) Differential HSTL-12 Class II is supported only in column I/O banks.
March 2016 Altera Corporation
and Table 6–7 summarize which I/O banks support these I/O standards in
I/O Bank Location
1,2,5,6
All
1,2,5,6
3,4,7,8
All
1,2,5,6
All
1,2,5,6
All
All
All
All
All
All
All
All
depend on system topology and performance requirement.
External Resistor
Transmitter (TX)
Network at Transmitter
Not Required
Three Resistors
Not Required
Three Resistors
Single Resistor
Not Required
Three Resistors
Not Required
Three Resistors
Single Resistor
—
—
—
—
—
—
6–25
Receiver (RX)
v v
v
—
v
—
v
—
v v
v
—
v v
v v
v v
v v
v v
Cyclone IV Device Handbook,
Volume 1