Altera Cyclone IV Device Handbook page 331

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
■ transmitter in electrical idle
■ receiver signal detect
receiver spread spectrum clocking
■
Low-Latency PCS Operation
When configured in low-latency PCS operation, the following blocks in the
transceiver PCS are bypassed, resulting in a lower latency PCS datapath:
■ 8B/10B encoder and decoder
■ word aligner
■ rate match FIFO
byte ordering
■
Figure 1–47
PCS operation.
.
Figure 1–47. Transceiver Channel Datapath in Basic Mode with Low-Latency PCS Operation
FPGA
Fabric
Transmitter in Electrical Idle
The transmitter buffer supports electrical idle state, where when enabled, the
differential output buffer driver is tri-stated. During electrical idle, the output buffer
assumes the common mode output voltage levels. For details about the electrical idle
features, refer to
1
The transmitter in electrical idle feature is required for compliance to the version 2.00
of PHY Interface for the PCI Express (PIPE) Architecture specification for PCIe
protocol implementation.
Signal Detect at Receiver
Signal detect at receiver is only supported when 8B/10B encoder/decoder block is
enabled.
February 2015 Altera Corporation
shows the transceiver channel datapath in Basic mode with low-latency
Tx Phase
Comp
Byte Serializer
FIFO
wr_clk rd_clk wr_clk
Rx
Byte Byte
Phase
Order- De-
Comp
serializer
ing
FIFO
"PCI Express (PIPE) Mode" on page
Transmitter Channel PCS
8B/10B Encoder
rd_clk
Receiver Channel PCS
Rate
8B/10B Deskew
Match
Decoder FIFO
FIFO
1–52.
1–51
Transmitter Channel PMA
Serializer
Receiver Channel PMA
Word Deserial-
CDR
Aligner
izer
Cyclone IV Device Handbook,
Volume 2