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Table 6–4. Number of VREF Pins Per I/O Bank for Cyclone IV E Devices (Part 2 of 2)
I/O
Bank
(1)
8
1
1
1
1
1
1
Note to
Table
6–4:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
Table 6–5. Number of VREF Pins Per I/O Bank for Cyclone IV GX Devices
Device
4CGX15
4CGX22
I/O Bank
(1)
3
1
1
4
1
1
5
1
1
6
1
1
7
1
1
(2)
8
1
1
Notes to
Table
6–5:
(1) User I/O pins are used as inputs or outputs; clock input pins are used as inputs only; clock output pins are used as output only.
(2) Bank 9 does not have VREF pin. If input pins with VREF I/O standards are used in bank 9 during user mode, it shares the VREF pin in bank 8.
Each Cyclone IV I/O bank has its own VCCIO pins. Each I/O bank can support only one V
2.5, 3.0, or 3.3 V. Any number of supported single-ended or differential standards can be simultaneously supported in a single
I/O bank, as long as they use the same V
2
2
2
2
2
2
1
4CGX30
4CGX50
1
3
1
3
1
3
1
3
1
3
1
3
levels for input and output pins.
CCIO
1
1
4
4
4
4
4
4CGX75
3
3
3
3
3
3
3
3
3
3
3
3
4
4
2
2
2
3
3
4CGX110
4CGX150
3
3
3
3
3
3
3
3
3
3
3
3
setting from among 1.2, 1.5, 1.8,
CCIO
3
3
3
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