Altera Cyclone IV Device Handbook page 293

Chapter 1: Cyclone IV Transceivers Architecture
Receiver Channel Datapath
In a DC-coupled link, the transmitter DC common mode voltage is seen unblocked at
the receiver input buffer as shown in
depends on the transmitter common mode voltage and the receiver common mode
voltage. When using the receiver OCT and on-chip biasing circuitry in a DC coupled
link, you must ensure the transmitter common mode voltage is compatible with the
receiver common mode requirements. If you disable the OCT, you must terminate and
bias the receiver externally and ensure compatibility between the transmitter and the
receiver common mode voltage.
Figure 1–13. DC-Coupled Link with OCT
Figure 1–14
Figure 1–14. Receiver Input Buffer Block Diagram
The receiver input buffers support the following features:
February 2015 Altera Corporation
Transmitter
TX Termination
TX
V
CM
shows the receiver input buffer block diagram.
Receiver Input Buffer
rx_datain
50 or 75 
50  or 75 
RX
V
CM
Figure 1–13. The link common mode voltage
Physical Medium
Physical Medium
RX
V
CM
Equalization
and
DC Gain
Circuitry
Signal
Threshold
Detection
Circuitry
1–13
Receiver
RX Termination
To CDR
Signal
Detect
Cyclone IV Device Handbook,
Volume 2