Altera Cyclone IV Device Handbook page 132

6–26
Table 6–7. Differential I/O Standards Supported in Cyclone IV GX I/O Banks
Differential I/O Standards
LVDS
RSDS
mini-LVDS
PPDS
(1)
BLVDS
(2)
LVPECL
(3)
Differential SSTL-2
(3)
Differential SSTL-18
(3)
Differential HSTL-18
(3)
Differential HSTL-15
(3)
Differential HSTL-12
Notes to Table 6–7:
(1) Transmitter and Receiver f
MAX
(2) The LVPECL I/O standard is only supported on dedicated clock input pins.
(3) The differential SSTL-2, SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards are only supported on clock input pins and PLL output clock
pins. PLL output clock pins do not support Class II interface type of differential SSTL-18, HSTL-18, HSTL-15, and HSTL-12 I/O standards.
You can use I/O pins and internal logic to implement a high-speed differential
interface in Cyclone IV devices. Cyclone IV devices do not contain dedicated
serialization or deserialization circuitry. Therefore, shift registers, internal
phase-locked loops (PLLs), and I/O cells are used to perform serial-to-parallel
conversions on incoming data and parallel-to-serial conversion on outgoing data. The
differential interface data serializers and deserializers (SERDES) are automatically
constructed in the core logic elements (LEs) with the Quartus II software ALTLVDS
megafunction.
Cyclone IV Device Handbook,
Volume 1
I/O Bank Location
5,6
3,4,5,6,7,8
5,6
3,4,7,8
3,4,5,6,7,8
5,6
3,4,5,6,7,8
5,6
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
3,4,5,6,7,8
4,5,6,7,8
depend on system topology and performance requirement.
Chapter 6: I/O Features in Cyclone IV Devices
External Resistor
Network at Transmitter (TX)
Transmitter
Not Required
Three Resistors
Not Required
Three Resistors
Single Resistor
Not Required
Three Resistors
Not Required
Three Resistors
Single Resistor
—
—
—
—
—
—
High-Speed I/O Interface
Receiver (RX)
v v
v
—
v
—
v
—
v v
v
—
v v
v v
v v
v v
v v
March 2016 Altera Corporation