Altera Cyclone IV Device Handbook page 320

1–40
When the byte serializer is enabled, the common bonded low-speed clock frequency is
halved before feeding to the read clock of TX phase compensation FIFO. The common
bonded low-speed clock is available in FPGA fabric as coreclkout port, which can be
used in FPGA fabric to send transmitter data and control signals to the bonded
channels.
Figure 1–38. Transmitter Only Datapath Clocking in Bonded Channel Configuration
FPGA
Fabric
tx_coreclk[3]
tx_coreclk[2]
coreclkout
tx_coreclk[1]
tx_coreclk[0]
1
Bonded channel configuration is not available for Receiver Only channel operation
because each of the channels are individually clocked by its recovered clock.
Cyclone IV Device Handbook,
Volume 2
Tx Phase
Comp
FIFO
wr_clk rd_clk
Tx Phase
Comp
FIFO
wr_clk rd_clk
/2
Tx Phase
Comp
FIFO
wr_clk rd_clk
Tx Phase
Comp
FIFO
wr_clk rd_clk
Chapter 1: Cyclone IV Transceivers Architecture
Transmitter Channel PCS 3
8B/10B Encoder
Byte Serializer
wr_clk rd_clk
/2
Transmitter Channel PCS 2
8B/10B Encoder
Byte Serializer
wr_clk rd_clk
/2
Transmitter Channel PCS 1
8B/10B Encoder
Byte Serializer
wr_clk rd_clk
/2
Transmitter Channel PCS 0
8B/10B Encoder
Byte Serializer
wr_clk rd_clk
/2
Transceiver Clocking Architecture
Transmitter Channel PMA 3
Serializer
Transmitter Channel PMA 2
Serializer
Transmitter Channel PMA 1
Serializer
Transmitter Channel PMA 0
Serializer
In 2 Bonded Channel Configuration
In 4 Bonded Channel Configuration
February 2015 Altera Corporation
high-speed
clock
high-speed
clock
high-speed
clock
low-speed clock
high-speed
clock