Periphery Performance - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–29
Table 1–29. Active Configuration Mode Specifications for Cyclone IV Devices
Programming Mode
Active Parallel (AP)
Active Serial (AS)
Note to
(1) AP configuration mode is only supported for Cyclone IV E devices.
Table 1–30
Table 1–30. JTAG Timing Parameters for Cyclone IV Devices
Symbol
t
JCP
t
JCH
t
JCL
t
JPSU_TDI
t
JPSU_TMS
t
JPH
t
JPCO
t
JPZX
t
JPXZ
t
JSSU
t
JSH
t
JSCO
t
JSZX
t
JSXZ
Notes to
(1) For more information about JTAG waveforms, refer to
(2) The specification is shown for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins. For 1.8-V
(3) For EP4CGX22, EP4CGX30 (F324 and smaller package), EP4CGX110, and EP4CGX150 devices, the output time

Periphery Performance

This section describes periphery performance, including high-speed I/O and external
memory interface.
I/O performance supports several system interfaces, such as the high-speed I/O
interface, external memory interface, and the PCI/PCI-X bus interface. I/Os using the
SSTL-18 Class I termination standard can achieve up to the stated DDR2 SDRAM
interfacing speeds. I/Os using general-purpose I/O standards such as 3.3-, 3.0-, 2.5-,
1.8-, or 1.5-LVTTL/LVCMOS are capable of a typical 200 MHz interfacing frequency
with a 10 pF load.
December 2016 Altera Corporation
lists the active configuration mode specifications for Cyclone IV devices.
(1)
Table 1–29:
lists the JTAG timing parameters and values for Cyclone IV devices.
TCK clock period
TCK clock high time
TCK clock low time
JTAG port setup time for TDI
JTAG port setup time for TMS
JTAG port hold time
JTAG port clock to output
JTAG port high impedance to valid output
JTAG port valid output to high impedance
Capture register setup time
Capture register hold time
Update register clock to output
Update register high impedance to valid output
Update register valid output to high impedance
Table 1–30:
LVTTL/LVCMOS and 1.5-V LVCMOS, the output time specification is 16 ns.
specification for 3.3-, 3.0-, and 2.5-V LVTTL/LVCMOS operation of JTAG pins is 16 ns. For 1.8-V LVTTL/LVCMOS
and 1.5-V LVCMOS, the output time specification is 18 ns.
DCLK Range Typical DCLK
20 to 40
20 to 40
Parameter
(2), (3)
(2), (3)
(2), (3)
"JTAG Waveform"
Unit
33 MHz
33 MHz
(1)
Min Max
40 —
19 —
19 —
1 —
3 —
10 —
— 15
— 15
— 15
5 —
10 —
— 25
— 25
— 25
in "Glossary" on page 1–37.
Cyclone IV Device Handbook,
1–27
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Volume 3