Altera Cyclone IV Device Handbook page 159

Chapter 7: External Memory Interfaces in Cyclone IV Devices
Cyclone IV Devices Memory Interfaces Features
Figure 7–7
Figure 7–7. Cyclone IV DDR Input Registers
These DDR input registers are implemented in the core of devices. The DDR data is
first fed to two registers, input register A
■ Input register A
■ Input register B
■ Register C
The data from the DDR input register is fed to two registers, sync_reg_h and
sync_reg_l, then the data is typically transferred to a FIFO block to synchronize the
two data streams to the rising edge of the system clock. Because the read-capture
clock is generated by the PLL, the read-data strobe signal (DQS or CQ) is not used
during read operation in Cyclone IV devices; hence, postamble is not a concern in this
case.
March 2016 Altera Corporation
illustrates Cyclone IV DDR input registers.
dataout_h
dataout_l
Register C
captures the DDR data present during the rising edge of the clock
I
captures the DDR data present during the falling edge of the clock
I
aligns the data before it is synchronized with the system clock
I
DDR Input Registers in Cyclone IV Device
LE
Register
Input Register A
I
neg_reg_out
LE LE
Register Register
Input Register B
I I
and input register B
I
7–13
DQ
Capture Clock
PLL
.
I
Cyclone IV Device Handbook,
Volume 1