8–30
Figure 8–11
interfaces to minimize signal integrity issues.
Figure 8–11. Balanced Star Routing
Notes to
(1) Altera recommends that M does not exceed 6 inches, as listed in
(2) Altera recommends using a balanced star routing. Keep the N length equal and as short as possible to minimize
reflection noise from the transmission line. The M length is applicable for this setup.
Estimating AP Configuration Time
AP configuration time is dominated by the time it takes to transfer data from the
parallel flash to Cyclone IV E devices. This parallel interface is clocked by the
Cyclone IV E DCLK output (generated from an internal oscillator). The DCLK minimum
frequency when using the 40-MHz oscillator is 20 MHz (50 ns). In word-wide cascade
programming, the DATA[15..0] bus transfers a 16-bit word and essentially cuts
configuration time to approximately 1/16 of the AS configuration time.
and
Equation 8–4.
Size
Equation 8–5.
Cyclone IV Device Handbook,
Volume 1
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
shows the recommended balanced star routing for multiple bus master
DCLK
Cyclone IV E
Master Device
Figure
8–11:
Equation 8–5
show the configuration time calculations.
maximum DCLK period
----------------------------------------------------------------
16 bits per DCLK cycle
9,600,000 bits
M (1)
Table 8–11 on page
estimated maximum configuration time
=
50 ns
------------- -
=
30 ms
16 bit
Configuration
External
Master Device
N (2)
N (2)
Micron Flash
8–28.
Equation 8–4
May 2013 Altera Corporation
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