Functional Simulation Of The Dynamic Reconfiguration Process; Document Revision History - Altera Cyclone IV Device Handbook

Chapter 3: Cyclone IV Dynamic Reconfiguration

Functional Simulation of the Dynamic Reconfiguration Process

Functional Simulation of the Dynamic Reconfiguration Process
This section describes the points to be considered during functional simulation of the
dynamic reconfiguration process.
■ You must connect the ALTGX_RECONFIG instance to the
ALTGX_instance/ALTGX instances in your design for functional simulation.
The functional simulation uses a reduced timing model of the dynamic
■
reconfiguration controller. The duration of the offset cancellation process is 16
reconfig_clk clock cycles for functional simulation only.
■ The gxb_powerdown signal must not be asserted during the offset cancellation
sequence (for functional simulation and silicon).

Document Revision History

Table 3–8
Table 3–8. Document Revision History
Date Version
November 2011 2.1
December 2010 2.0
July 2010 1.0
November 2011 Altera Corporation
lists the revision history for this chapter.
Updated "Dynamic Reconfiguration Controller
■
Reconfiguration Mode",
Dynamic Reconfiguration"
Updated Table 3–2 and
■
Updated for the Quartus II software version 10.1 release.
■
Updated Table 3–1, Table 3–2, Table 3–3, Table 3–4, Table 3–5, and Table 3–6.
■
Added Table 3–7.
■
Updated Figure 3–1, Figure 3–11, Figure 3–13, and Figure 3–14.
■
Updated "Offset Cancellation Feature", "Error Indication During Dynamic
■
Reconfiguration", "Data Rate Reconfiguration Mode Using RX Local Divider", "PMA
Controls Reconfiguration Mode", and "Control and Status Signals for Channel
Reconfiguration" sections.
Initial release.
Changes
Architecture",
"PLL Reconfiguration Mode", and
sections.
Table 3–4.
3–37
"PMA Controls
"Error Indication During
Cyclone IV Device Handbook,
Volume 2