Altera Cyclone IV Device Handbook page 282

1–2
1
The Cyclone IV GX device includes a hard intellectual property (IP) implementation
of the PCIe MegaCore
configured in the root port or endpoint mode. For more information, refer to
Express Hard IP Block" on page
Transceiver Architecture
Cyclone IV GX devices offer either one or two transceiver blocks per device,
depending on the package. Each block consists of four full-duplex (transmitter and
receiver) channels, located on the left side of the device (in a die-top view).
and
locations in Cyclone IV GX devices.
Figure 1–1. F324 and Smaller Packages with Transceiver Channels for Cyclone IV GX Devices
Note to
(1) Channel 2 and Channel 3 are not available in the F169 and smaller packages.
Cyclone IV Device Handbook,
Volume 2
®
functions, supporting Gen1 ×1, ×2, and ×4 initial lane widths
Figure 1–2 show the die-top view of the transceiver block and related resource
Transceiver
Block GXBL0
Figure 1–1:
Chapter 1: Cyclone IV Transceivers Architecture
1–46.
MPLL_2
Channel 3 (1)
Channel 2 (1) PCIe
hard IP
Channel 1
Channel 0
Calibration Block
MPLL_1
Transceiver Architecture
"PCI-
Figure 1–1
F324 and smaller
packages
February 2015 Altera Corporation