Gclk Network - Altera Cyclone IV Device Handbook

5–2
f
For more information about the number of GCLK networks in each device density,
refer to the

GCLK Network

GCLKs drive throughout the entire device, feeding all device quadrants. All resources
in the device (I/O elements, logic array blocks (LABs), dedicated multiplier blocks,
and M9K memory blocks) can use GCLKs as clock sources. Use these clock network
resources for control signals, such as clock enables and clears fed by an external pin.
Internal logic can also drive GCLKs for internally generated GCLKs and
asynchronous clears, clock enables, or other control signals with high fan-out.
Table
clock sources to the GCLK networks.
Table 5–1. GCLK Network Connections for EP4CGX15, EP4CGX22, and EP4CGX30
GCLK Network Clock
Sources
— — — — —
CLK4/DIFFCLK_2n
— — — — — —
CLK5/DIFFCLK_2p
— — — — — —
CLK6/DIFFCLK_3n
— — — — —
CLK7/DIFFCLK_3p
— — — — — — — — — —
CLK8/DIFFCLK_5n
— — — — — — — — — — —
CLK9/DIFFCLK_5p
CLK10/DIFFCLK_4n/RE
— — — — — — — — — — —
FCLK1n
CLK11/DIFFCLK_4p/RE
— — — — — — — — — —
FCLK1p
CLK12/DIFFCLK_7p/RE
— — — — — — — — — — — — — — —
FCLK0p
CLK13/DIFFCLK_7n/RE
— — — — — — — — — — — — — — — —
FCLK0n
— — — — — — — — — — — — — — — —
CLK14/DIFFCLK_6p
— — — — — — — — — — — — — — —
CLK15/DIFFCLK_6n
v
PLL_1_C0
—
PLL_1_C1
v
PLL_1_C2
—
PLL_1_C3
— —
PLL_1_C4
v
PLL_2_C0
—
PLL_2_C1
v
PLL_2_C2
—
PLL_2_C3
— —
PLL_2_C4
— — — — —
PLL_3_C0
Cyclone IV Device Handbook,
Volume 1
Cyclone IV FPGA Device Family Overview
5–1, Table 5–2 on page
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Chapter 5: Clock Networks and PLLs in Cyclone IV Devices
chapter.
5–4, and Table 5–3 on page 5–7
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GCLK Networks
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Clock Networks
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