Reference Information - Altera Cyclone IV Device Handbook

Chapter 2: Cyclone IV Reset Control and Power Down

Reference Information

■ In PCIe mode simulation, you must assert the tx_forceelecidle signal for at least
one parallel clock cycle before transmitting normal data for correct simulation
behavior.
Reference Information
For more information about some useful reference terms used in this chapter, refer to
the links listed in
Table 2–7. Reference Information
Automatic Lock Mode
Bonded channel configuration
busy
Dynamic Reconfiguration Reset Sequences
gxb_powerdown
LTD
LTR
Manual Lock Mode
Non-Bonded channel configuration
PCIe
pll_locked
pll_areset
rx_analogreset
rx_digitalreset
rx_freqlocked
tx_digitalreset
September 2014 Altera Corporation
Table 2–7.
Terms Used in this Chapter Useful Reference Points
page 2–8
page 2–6
page 2–3
page 2–19
page 2–3
page 2–6
page 2–6
page 2–9
page 2–10
page 2–17
page 2–3
page 2–3
page 2–2
page 2–2
page 2–3
page 2–2
Cyclone IV Device Handbook,
2–23
Volume 2