Altera Cyclone IV Device Handbook page 182

8–18
Altera recommends putting a buffer before the DATA and DCLK output from the master
device to avoid signal strength and signal integrity issues. The buffer must not
significantly change the DATA-to-DCLK relationships or delay them with respect to other
AS signals (ASDI and nCS). Also, the buffer must only drive the slave devices to ensure
that the timing between the master device and the serial configuration device is
unaffected.
This configuration method supports both compressed and uncompressed .sof.
Therefore, if the configuration bitstream size exceeds the capacity of a serial
configuration device, you can enable the compression feature in the .sof or you can
select a larger serial configuration device.
Guidelines for Connecting a Serial Configuration Device to Cyclone IV
Devices for an AS Interface
For single- and multi-device AS configurations, the board trace length and loading
between the supported serial configuration device and Cyclone IV device must follow
the recommendations listed in
Table 8–7. Maximum Trace Length and Loading for AS Configuration
Cyclone IV
Device AS Pins
Note to
(1) For multi-devices AS configuration using Cyclone IV E with 1,0 V core voltage, the maximum board trace-length
Estimating AS Configuration Time
AS configuration time is dominated by the time it takes to transfer data from the serial
configuration device to the Cyclone IV device. This serial interface is clocked by the
Cyclone IV device DCLK output (generated from a 40-MHz internal oscillator for
Cyclone IV E devices, a 20- or 40-MHz internal oscillator, or an external CLKUSR of up
to 40 MHz for Cyclone IV GX devices).
Equation 8–2
Equation 8–2.
Size
Equation 8–3.
9,600,000 bits
Cyclone IV Device Handbook,
Volume 1
Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Maximum Board Trace Length from a
Cyclone IV Device to a Serial Configuration
Cyclone IV E
10
DCLK
10
DATA[0]
10
nCSO
10
ASDO
Table 8–7:
from the serial configuration device to the junction-split on both DCLK and Data0 line is 3.5 inches.
and Equation 8–3

maximum DCLK period

----------------------------------------------------------------

1 bit
 
50 ns

------------ -
= 480 ms
 
1 bit
Table 8–7.
Device (Inches)
Cyclone IV GX
6
6
6
6
show the configuration time calculations.

estimated maximum configuration ti
=

Configuration
Maximum Board Load (pF)
15
30
30
30
May 2013 Altera Corporation