Altera Cyclone IV Device Handbook page 471

Chapter 1: Cyclone IV Device Datasheet
Switching Characteristics
Table 1–25. PLL Specifications for Cyclone IV Devices
Symbol
t
DLOCK
(6)
t
OUTJITTER_PERIOD_DEDCLK
(6)
t
OUTJITTER_CCJ_DEDCLK
(6)
t
OUTJITTER_PERIOD_IO
(6)
t
OUTJITTER_CCJ_IO
t
PLL_PSERR
t
ARESET
t
CONFIGPLL
f
SCANCLK
t
CASC_OUTJITTER_PERIOD_DEDCLK
(8), (9)
Notes to Table 1–25:
(1) This table is applicable for general purpose PLLs and multipurpose PLLs.
(2) You must connect V
CCD_PLL
(3) This parameter is limited in the Quartus II software by the I/O maximum frequency. The maximum I/O frequency is different for each I/O
standard.
(4) The V frequency reported by the Quartus II software in the PLL Summary section of the compilation report takes into consideration the V
CO
post-scale counter K value. Therefore, if the counter K has a value of 2, the frequency reported can be lower than the f
(5) A high input jitter directly affects the PLL output jitter. To have low PLL output clock jitter, you must provide a clean clock source that is less
than 200 ps.
(6) Peak-to-peak jitter with a probability level of 10
to the intrinsic jitter of the PLL when an input jitter of 30 ps is applied.
(7) With 100-MHz scanclk frequency.
(8) The cascaded PLLs specification is applicable only with the following conditions:
Upstream PLL—0.59 MHz  Upstream PLL bandwidth < 1 MHz
■
Downstream PLL—Downstream PLL bandwidth > 2 MHz
■
(9) PLL cascading is not supported for transceiver applications.
December 2016 Altera Corporation
Parameter
Time required to lock dynamically (after switchover,
reconfiguring any non-post-scale counters/delays or
areset is deasserted)
Dedicated clock output period jitter
 100 MHz
F
OUT
F < 100 MHz
OUT
Dedicated clock output cycle-to-cycle jitter
 100 MHz
F
OUT
F < 100 MHz
OUT
Regular I/O period jitter
 100 MHz
F
OUT
F < 100 MHz
OUT
Regular I/O cycle-to-cycle jitter
 100 MHz
F
OUT
F < 100 MHz
OUT
Accuracy of PLL phase shift
Minimum pulse width on areset signal.
Time required to reconfigure scan chains for PLLs
scanclk frequency
Period jitter for dedicated clock output in cascaded
 100 MHz)
PLLs (F
OUT
Period jitter for dedicated clock output in cascaded
 100 MHz)
PLLs (F
OUT
to V through the decoupling capacitor and ferrite bead.
CCINT
–12
(14 sigma, 99.99999999974404% confidence level). The output jitter specification applies
(1), (2)
(Part 2 of 2)
Min Typ Max Unit
— — 1
— — 300
— — 30 mUI
— — 300
— — 30 mUI
— — 650
— — 75 mUI
— — 650
— — 75 mUI
— — ±50
10 — —
SCANCLK
(7)
— 3.5 —
cycles
— — 100 MHz
— — 425
— — 42.5 mUI
specification.
VCO
Cyclone IV Device Handbook,
Volume 3
1–25
ms
ps
ps
ps
ps
ps
ns
ps
CO