Serial Rapidio Mode - Altera Cyclone IV Device Handbook

1–64
Figure 1–59
symbol must be inserted. Because the rate match FIFO can only insert /I2/ ordered
sets, it inserts one /I2/ ordered set (two symbols inserted).
Figure 1–59. Example of Rate Match FIFO Insertion in GIGE Mode
1
The rate match FIFO does not insert or delete code groups automatically to overcome
FIFO empty or full conditions. In this case, the rate match FIFO asserts the
rx_rmfifofull and rx_rmfifoempty flags for at least two recovered clock cycles to
indicate rate match FIFO full and empty conditions, respectively. You must then assert
the rx_digitalreset signal to reset the receiver PCS blocks.

Serial RapidIO Mode

Serial RapidIO mode provides the non-bonded (×1) transceiver channel datapath
configuration for SRIO protocol implementation. The Cyclone IV GX transceiver
provides the PMA and the following PCS functions:
■ 8B/10B encoding and decoding
■ lane synchronization state machine
1
Cyclone IV GX transceivers do not have built-in support for some PCS functions such
as pseudo-random idle sequence generation and lane alignment in ×4 bonded
channel configuration. If required, you must implement these functions in a user
logics or external circuits.
The RapidIO Trade Association defines a high-performance, packet-switched
interconnect standard to pass data and control information between microprocessors,
digital signals, communications, network processes, system memories, and peripheral
devices. The SRIO physical layer specification defines serial protocol running at
1.25 Gbps, 2.5 Gbps, and 3.125 Gbps in either single-lane (×1) or bonded four-lane (×4)
at each line rate. Cyclone IV GX transceivers support single-lane (×1) configuration at
all three line rates. Four ×1 channels configured in Serial RapidIO mode can be
instantiated to achieve one non-bonded ×4 SRIO link. When implementing four ×1
SRIO channels, the receivers do not have lane alignment or deskew capability.
Cyclone IV Device Handbook,
Volume 2
shows an example of rate match FIFO insertion in the case where one
datain Dx.y
dataout Dx.y
rx_rmfifodatainserted
Chapter 1: Cyclone IV Transceivers Architecture
First /I2/ Second /I2/
Ordered Set Ordered Set
K28.5 D16.2 K28.5 D16.2
K28.5 D16.2 K28.5 D16.2
Transceiver Functional Modes
K28.5 D16.2 Dx.y
February 2015 Altera Corporation