Device Resources - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV FPGA Device Family Overview

Device Resources

■ Up to 532 user I/Os
■
■
■
■ Up to eight phase-locked loops (PLLs) per device
■ Offered in commercial and industrial temperature grades
Device Resources
Table 1–1
Table 1–1. Resources for the Cyclone IV E Device Family
Resources
Logic elements (LEs) 6,272
Embedded memory
(Kbits)
Embedded 18 × 18
multipliers
General-purpose PLLs
Global Clock Networks
User I/O Banks
(1)
Maximum user I/O
Note to Table 1–1:
(1) The user I/Os count from pin-out files includes all general purpose I/O, dedicated clock pins, and dual purpose configuration pins. Transceiver
pins and dedicated configuration pins are not included in the pin count.
March 2016 Altera Corporation
LVDS interfaces up to 840 Mbps transmitter (Tx), 875 Mbps Rx
Support for DDR2 SDRAM interfaces up to 200 MHz
Support for QDRII SRAM and DDR SDRAM up to 167 MHz
lists Cyclone IV E device resources.
10,320 15,408
270 414 504
15 23 56
2 2 4
10 10 20
8 8 8
179 179 343
22,320 28,848 39,600
594 594 1,134
66 66 116
4 4 4
20 20 20
8 8 8
153 532 532
55,856 75,408 114,480
2,340 2,745 3,888
154 200 266
4 4 4
20 20 20
8 8 8
374 426 528
Cyclone IV Device Handbook,
Volume 1
1–3