Altera Cyclone IV Device Handbook page 369

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Top-Level Port Lists
Table 1–27. Receiver Ports in ALTGX Megafunction for Cyclone IV GX (Part 3 of 3)
Block Port Name
rx_coreclk
rx_phase_comp_fifo
_error
RX PCS
rx_bitslipboundarys
electout
rx_datain
rx_freqlocked
rx_locktodata
rx_locktorefclk
RX PMA
rx_signaldetect
rx_recovclkout
February 2015 Altera Corporation
Input/
Clock Domain
Output
Output Clock signal
Synchronous to tx_clkout
Output (non-bonded modes) or
coreclkout (bonded modes)
Output Asynchronous signal.
Input N/A
Output Asynchronous signal
Input Asynchronous signal
Input Asynchronous signal
Output Asynchronous signal
Output Clock signal
Description
Optional read clock port for the RX phase compensation
FIFO.
RX phase compensation FIFO full or empty indicator.
A high level indicates FIFO is either full or empty.
■
Indicate the number of bits slipped in the word aligner
configured in manual alignment mode.
Values range from 0 to 9.
■
Receiver serial data input port.
Receiver CDR lock state indicator
A high level indicates the CDR is in LTD state.
■
A low level indicates the CDR is in LTR state.
■
Receiver CDR LTD state control signal
A high level forces the CDR to LTD state
■
When deasserted, the receiver CDR lock state
■
depends on the rx_locktorefclk signal level.
Receiver CDR LTR state control signal.
The rx_locktorefclk and rx_locktodata
■
signals control whether the receiver CDR states as
follows:
[rx_locktodata:rx_locktorefclk]
2'b00—receiver CDR is in automatic lock mode
■
2b'01—receiver CDR is in manual lock mode (LTR
■
state)
2b'1x—receiver CDR is in manual lock mode (LTD
■
state)
Signal threshold detect indicator.
Available in Basic mode when 8B/10B
■
encoder/decoder is used, and in PIPE mode.
A high level indicates that the signal present at the
■
receiver input buffer is above the programmed signal
detection threshold value.
CDR low-speed recovered clock
Only available in the GIGE mode for applications such
■
as Synchronous Ethernet.
Cyclone IV Device Handbook,
1–89
Volume 2