Lane Synchronization - Altera Cyclone IV Device Handbook

1–66
Figure 1–61
Figure 1–61. Transceiver Configuration in Serial RapidIO Mode

Lane Synchronization

In Serial RapidIO mode, the word aligner is compliant to the SRIO Specification 1.3
and is configured in automatic synchronization state machine mode with the
parameter settings as listed in
Table 1–20. Synchronization State Machine Parameters
Number of valid synchronization (/K28.5/) code groups received to achieve
synchronization
Number of erroneous code groups received to lose synchronization
Number of continuous good code groups received to reduce the error count by
one
Note to
(1) The word aligner supports 10-bit pattern lengths in SRIO mode.
Cyclone IV Device Handbook,
Volume 2
shows the transceiver configuration in Serial RapidIO mode.
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Data Rate (Gbps)
Byte Ordering
FPGA Fabric-to-Transceiver
Interface Width
FPGA Fabric-to-Transceiver
Interface Frequency (MHz)
Table
Parameter
Table 1–20:
Chapter 1: Cyclone IV Transceivers Architecture
SRIO
×1
Disabled
Automatic Synchronization
State Machine (10-Bit)
Enabled
Enabled
Enabled
1.25/2.5/
3.125
Disabled
16-Bit
62.5/125/
156.25
1–20.
(1)
Transceiver Functional Modes
Disabled
Enabled
1.25/2.5/
3.125
Disabled
16-Bit
62.5/125/
156.25
Value
127
3
255
February 2015 Altera Corporation