Altera Cyclone IV Device Handbook page 427

Chapter 3: Cyclone IV Dynamic Reconfiguration
Dynamic Reconfiguration Modes
■ Enable this option if you want tx_clkout of the first channel (channel 0) of the
transceiver block to provide the write clock to the Transmitter Phase
Compensation FIFOs of the remaining channels in the transceiver block.
This option is typically enabled when all the channels of a transceiver block have
■
the same functional mode and data rate and are reconfigured to the identical
functional mode and data rate.
Figure 3–11
channels of a transceiver block.
Figure 3–11. Option 1 for Transmitter Core Clocking (Channel Reconfiguration Mode)
FPGA Fabric
tx_clkout[0]
Low-speed parallel clock (tx_clkout0)
High-speed serial clock generated by the MPLL
November 2011 Altera Corporation
Option 1: Share a Single Transmitter Core Clock Between Transmitters
shows the sharing of channel 0's tx_clkout between all four regular
Transceiver Block
TX0
RX0
TX1
RX1
TX2
RX2
TX3
RX3
3–29
MPLL
Cyclone IV Device Handbook,
Volume 2