Altera Cyclone IV Device Handbook page 298

1–18
After updating the word boundary, word aligner status signals (rx_syncstatus and
rx_patterndetect) are driven high for one parallel clock cycle synchronous to the
most significant byte of the word alignment pattern. The rx_syncstatus and
rx_patterndetect signals have the same latency as the datapath and are forwarded to
the FPGA fabric to indicate the word aligner status. Any word alignment pattern
received thereafter in the same word boundary causes only the rx_patterndetect
signal to go high for one clock cycle.
Figure 1–17
width mode. In this example, a /K28.5/ (10'b0101111100) is specified as the word
alignment pattern.
The word aligner aligns to the /K28.5/ alignment pattern (red) in cycle n because the
rx_enapatternalign signal is asserted high. The rx_syncstatus signal goes high for
one clock cycle indicating alignment to a new word boundary. The rx_patterndetect
signal also goes high for one clock cycle to indicate initial word alignment.
At time n + 1, the rx_enapatternalign signal is deasserted to instruct the word
aligner to lock the current word boundary.
The alignment pattern is detected again (green) in a new word boundary across cycles
n + 2 and n + 3. The word aligner does not align to this new word boundary because
the rx_enapatternalign signal is held low.
The /K28.5/ word alignment pattern is detected again (blue) in the current word
boundary during cycle n + 5 causing the rx_patterndetect signal to go high for one
parallel clock cycle.
Figure 1–17. Word Aligner in 10-bit Manual Alignment Mode
1
If the word alignment pattern is known to be unique and does not appear between
word boundaries, you can hold the rx_enapatternalign signal constantly high
because there is no possibility of false word alignment. If there is a possibility of the
word alignment pattern occurring across word boundaries, you must control the
rx_enapatternalign signal to lock the word boundary after the desired word
alignment is achieved to avoid re-alignment to an incorrect word boundary.
Cyclone IV Device Handbook,
Volume 2
shows the manual alignment mode word aligner operation in 10-bit data
n
rx_clock
rx_dataout[9..0]
111110000 0101111100 111110000 1111001010 1000000101 111110000 0101111100
MSB LSB
rx_enapatternalign
rx_patterndetect
rx_syncstatus
Chapter 1: Cyclone IV Transceivers Architecture
n + 1 n + 2 n + 3 n + 4
Receiver Channel Datapath
n + 5
MSB LSB
February 2015 Altera Corporation