Altera Cyclone IV Device Handbook page 175

Chapter 8: Configuration and Remote System Upgrades in Cyclone IV Devices
Configuration
This four-pin interface connects to Cyclone IV device pins, as shown in
Figure 8–2. Single-Device AS Configuration
Notes to
(1) Connect the pull-up resistors to the V
(2) Cyclone IV devices use the ASDO-to-ASDI path to control the configuration device.
(3) The nCEO pin is left unconnected or used as a user I/O pin when it does not feed the nCE pin of another device.
(4) The MSEL pin settings vary for different configuration voltage standards and POR time. To connect the MSEL pins,
refer to
to V
(5) Connect the series resistor at the near end of the serial configuration device.
(6) These pins are dual-purpose I/O pins. The nCSO pin functions as FLASH_nCE pin in AP mode. The ASDO pin functions
as the DATA[1] pin in AP and FPP modes.
(7) Only Cyclone IV GX devices have an option to select CLKUSR (40 MHz maximum) as the external clock source for
DCLK.
1
To tri-state the configuration bus for AS configuration schemes, you must tie nCE high
and nCONFIG low.
1
The 25- resistor at the near end of the serial configuration device for DATA[0] works
to minimize the driver impedance mismatch with the board trace and reduce the
overshoot seen at the Cyclone IV device DATA[0] input pin.
In the single-device AS configuration, the maximum board loading and board trace
length between the supported serial configuration device and the Cyclone IV device
must follow the recommendations in
The DCLK generated by the Cyclone IV device controls the entire configuration cycle
and provides timing for the serial interface. Cyclone IV devices use an internal
oscillator or an external clock source to generate the DCLK. For Cyclone IV E devices,
you can use a 40-MHz internal oscillator to generate the DCLK and for Cyclone IV GX
devices you can use a slow clock (20 MHz maximum) or a fast clock
(40 MHz maximum) from the internal oscillator or an external clock from CLKUSR to
generate the DCLK. There are some variations in the internal oscillator frequency
because of the process, voltage, and temperature (PVT) conditions in Cyclone IV
May 2013 Altera Corporation
V (1)
CCIO
10 kΩ
Serial Configuration
10 kΩ
Device
25 Ω (5)
DATA
DCLK
nCS
ASDI
Figure 8–2:
Table 8–3 on page 8–8, Table 8–4 on page
or GND.
CCA
V (1)
CCIO
V (1)
CCIO
10 kΩ
Cyclone IV Device
nSTATUS
CONF_DONE
nCONFIG
nCE
GND
DATA[0]
DCLK
nCSO (6)
ASDO (6)
(2)
supply of the bank in which the pin resides.
CCIO
8–8, and Table 8–5 on page
Table 8–7 on page
Figure 8–2.
N.C. (3)
nCEO
(7)
CLKUSR
MSEL[ ] (4)
8–9. Connect the MSEL pins directly
8–18.
Cyclone IV Device Handbook,
Volume 1
8–11