Registered Mode Phase Compensation Fifo - Altera Cyclone IV Device Handbook

Chapter 1: Cyclone IV Transceivers Architecture
Transceiver Functional Modes
Figure 1–67
Figure 1–67. Transceiver Configuration in Deterministic Latency Mode
Both CPRI and OBSAI protocols define the serial interface connecting the base station
component (specifically channel cards) and remote radio heads (specifically radio
frequency cards) in a radio base station system with fiber optics. The protocols require
the accuracy of round trip delay measurement for single-hop and multi-hop
connections to be within ± 16.276 ns. The Cyclone IV GX transceivers support the
following CPRI and OBSAI line rates using Deterministic Latency mode:
CPRI —614.4 Mbps, 1.2288 Gbps, 2.4576 Gbps, and 3.072 Gbps
■
■ OBSAI—768 Mbps, 1.536 Gbps, and 3.072 Gbps
f
For more information about deterministic latency implementation, refer to
Implementing Deterministic Latency for CPRI and OBSAI Protocols in Stratix IV, HardCopy
IV, Arria II GX, and Cyclone IV

Registered Mode Phase Compensation FIFO

In Deterministic Latency mode, the RX phase compensation FIFO is set to registered
mode while the TX phase compensation FIFO supports optional registered mode.
When set into registered mode, the phase compensation FIFO acts as a register and
eliminates the latency uncertainty through the FIFOs.
February 2015 Altera Corporation
shows the transceiver configuration in Deterministic Latency mode.
Functional Mode
Channel Bonding
Low-Latency PCS
Word Aligner (Pattern Length)
8B/10B Encoder/Decoder
Rate Match FIFO
Byte SERDES
Enabled
Data Rate (Gbps)
0.6-
3.125
Byte Ordering
Disabled
FPGA Fabric-to-Transceiver
Interface Width 16-Bit
FPGA Fabric-to-Transceiver
60-
Interface Frequency (MHz)
156.25
TX PCS Latency (FPGA
Fabric-Transceiver Interface
2.5 - 3.5
Clock Cycles)
RX PCS Latency (FPGA
Fabric-Transceiver Interface
5 - 6
Clock Cycles)
Deterministic Latency
×1, ×4
Disabled
Manual Alignment
(10-Bit)
Enabled Disabled
Disabled Disabled
Disabled Enabled Disabled
0.6- 0.6- 0.6-
1.5625 3.125 1.5625
Disabled Disabled Disabled
8-Bit 20-Bit 10-Bit
30- 60- 30-
156.25 156.25 156.25
4 - 5 2.5 - 3.5 4 - 5
8 - 9 5 - 6 8 - 9
Devices.
Bit Slip
(10-Bit)
Enabled Disabled
Disabled Disabled
Enabled Disabled Enabled Disabled
0.6- 0.6- 0.6- 0.6-
3.125 1.5625 3.125 1.5625
Disabled Disabled Disabled Disabled
16-Bit 8-Bit 20-Bit 10-Bit
60- 30- 60- 30-
156.25 156.25 156.25 156.25
2.5 - 3 4 2.5 - 3 4
5 - 6 8 - 9 5 - 6 8 - 9
AN 610:
Cyclone IV Device Handbook,
1–75
Volume 2